Many data processing systems contain multiple bus masters. Bus arbitration logic is typically used to select one out of the several requesting masters. The selected request will then gain bus mastership. The selection may be made in any of a number of ways, including, round-robin, fairness, strict priority, or any of a number of selection methods. Selection algorithms can range from the extremely complex to the extremely simple. Once a bus arbiter assigns bus mastership to a master, that master is said to "own" the bus.
In many systems a need arises for a master to hold ownership of the bus for the duration of several transfers. This holding of ownership is necessarily without interruption of ownership. It is often necessary to ensure an indivisible sequence of accesses for a given sequence of transfers. One example of the necessity of ownership holding is in a semaphore operation. Semaphore operations involve a series of read and write accesses. Typically, an indication is provided, such as a LOCK attribute, to an initial portion of the sequence of transfers. The indication prevents bus arbitration logic from reallocating ownership of the bus. Once locked, the current master holds ownership for the duration of the locked transfers.
Another example of necessary bus ownership holding is for a read-modify-write cycle. The read-modify-write cycle performs a sequence similar to the following steps: initially read a memory location, then conditionally modify the data in the arithmetic logic unit, and finally write the data out to the same memory location. Motorola Semiconductor located in Austin, Tx. produces several devices having these type of operations. In Motorola's MC68020 processor, the read-modify-write operation is indivisible, providing semaphore capabilities in multi-processor systems. During the entire read-modify-write sequence, the MC68020 asserts a signal to indicate that an indivisible operation is occurring. The MC68020 does not issue a bus grant (BG) signal in response to a bus request (BR) signal during this operation. The MC68020 has two instructions which utilize read-modify-write operations. The first is the test-and-set (TAS) and the second is the compare-and-swap (CAS).
Consider a simple system, having two possible bus masters. One of the masters is designated as the default bus master and a second master is designated as the higher priority master. The default bus master has the lowest priority and grants bus ownership to the higher priority master in response to receipt of a bus request. In this case bus arbitration logic is integrated into the lower priority master or default bus master. Upon request the bus is granted to the higher priority master.
When a sequence of indivisible accesses is required, granting of the bus is withheld until completion of the indivisible accesses associated with the instruction. An example is the TAS instruction where granting of the ownership of the bus to the other master is withheld until completion of all accesses associated with the TAS instruction. The granting of the bus is effectively blocked. The blocking is intrinsic in the TAS instruction. In other words, execution of the TAS instruction includes a block to the granting of bus ownership until completion of the TAS instruction. In each of these cases, granting of bus mastership is effectively locked until some criterion is satisfied.
Many CPUs have no explicit instruction which performs a locked sequence of accesses (i.e. a TAS type instruction), however, emulation of such a locked sequence is desirable. One implementation is in a LOCK/UNLOCK instruction. The LOCK/UNLOCK instruction causes the CPU to present a bus indicator or signal for interpretation by bus arbitration logic. The LOCK indication will allow the CPU to perform a sequence of indivisible accesses. The UNLOCK indicator will allow the bus arbiter to grant ownership to an alternate master.
Existing methods for allowing performance of a sequence of indivisible accesses prior to arbitration of the bus implement special instructions or external signals. Both of these methods require extra processor cycles to affect the bus blocking. It is desirable to implement a bus locking capability without the use of additional special instructions and/or external signals. The ability to implement a locking capability without additional external means will greatly simplify a data processing system.